SystemVerilog for Verification

Name of the course Online Lecture Exercises Lab
SystemVerilog for Verification

The course is an twelve-weeks training on the specific extensions of the SystemVerilog Hardware Description Language (HDL) for verification, a basic introduction to Cadence Specman Elite and the e-language. It is recommended for students with a solid knowledge in Digital Engineering and Object-Oriented Programming. The level and workload of the course depends on the study program.

The course is organized in two parts. Part One is a virtual classroom education on SystemVerilog for verification. Part Two is a laboratory, where students will first work on a prepared test environment and later build their own test environment to verify a digital design. Having completed the course on ASIC design with SystemVerilog is a substantial advantage but not an absolute must.

The course SystemVerilog for Verfication utilizes the Cadence Design Environment. The number of participants for the lab is limited to the number of available licences. It is a clear objective of the course to be an online course.

Some results from the laboratory work can be found here.

Candidates with a focus on digital design at register transfer level are invited to visit the course Digital Hardware design with SystemVerilog. Having completed the course successfully, students will be able to build a simple verification environment for constrained-random and corner-case verification.





Course content

Part Content Script*
1 SystemVerilog for verification [PDF*]
2 SystemVerilog for verification exercises [PDF*]
3 Cadence Specman Elits fundamentals and the IEEE 1647 e language [PDF*]
4 Cadence Specman Elite laboratory [PDF*]
*under work


Literature

[1] RTL Modeling with SystemVerilog for Simulation and Synthesis, Stuart Sutherland,
      published by Sutherland HDL, Oregon 2017, ISBN 078-1-5467-7634-5
[2] SystemVerilog for Verification, Spear and Tumbush,
      published by Springer Publications, 2012, ISBN 978-1-4899-9500-1