SystemVerilog for Verification

Name of the course Online Lecture Exercises Lab
SystemVerilog for Verification (✓) (✓)

'SystemVerilog for Verification' is a twelve-weeks training on the verification extensions of SystemVerilog, Specman and the e-Language. It is available for Bachelor programs in a basic version and Master programs in a professional version. The course is recommended for students with a background in Digital Engineering and Object-Oriented Programming. Level and workload of the course depends on the study program.

The course provides a virtual classroom education and a practical exercise. Students get first introduced to the general verification principles and techniques before they start with the practical exercise. They later build their own test environments and set up verification plans. Having completed the course SystemVerilog for Design is a substantial advantage to have the designer's perspective. The introduction to SystemVerilog is closely aligned to the book 'SystemVerilog for Verification' by Spear and Tumbush, 2012.

The basic version of the course is intended for Bachelor programs and based on a set of free tools, the Verilator C/C++ simulator and coverage analyzer and the GTKwave waveform viewer. Participants are provided with simple SystemVerilog designs and are supposed to create test benches, write assertions and track coverage and export simple verification reports. The professional version of the course is intended for Master Programs. The professional lab exercises utilize the Cadence Verification Environment, Specman and the e-Language. Participants work on a complex case study and see how components play together to build a complex layered verification environment. Some results from the laboratory work can be found here.

'SystemVerilog for Verification' is an online course to provide a maximum flexibility for participants on all levels of expertise, . Candidates with a focus on digital design at register transfer level are invited to visit the course SystemVerilog for Design.



Finish date: 10/2021


Course content

Part Content Script
1 Introduction to the Verification Methodology - Methodology Basics, Testbench Functionality, Randomization, Coverage, Performance [PDF]
2 Verification with SystemVerilog - Data Types, Arrays, Methods, Types and Type Conversions, User-Defined Structures, Packages, Streaming Operators, Enumeration Types [PDF]
3 Verification with SystemVerilog - Procedural Statements, Tasks and Functions, Arguments, Local Data Storage, Simulation Time and Delay [PDF]
4 Verification with SystemVerilog - Testbench and Design under Test, Interfaces, Stimulus, Driving and Sampling, Simulator Program, ATM-Router Example [PDF]
5 Verification with SystemVerilog - Object Oriented Programmin with SystemVerilog, Building a Testbench [PDF]
6 Verification with SystemVerilog - Introduction to Randomization, Constraints, Probabilities, Constraint Blocks, Randomization Problems, Random Scenarios, Random Device Control, Common Problems, Tips and Tricks [PDF]
7 Verification with SystemVerilog - Working with Threads, Events, Semaphores, Testbench with Threads and IPC [PDF*]
8 Verification with SystemVerilog - Functional Coverage, Types of Coverage, Strategies, Simple Functional Example, Analyzing Coverage Data [PDF*]
9 Introduction to Specman and the e-Language [PDF*]
10 Case-Study: Constrained random verification of an IEEE-754 floating point design with SystemVerilog, Specman and the e-Language [PDF*]
*under work


Literature

[1] SystemVerilog for Verification, Spear and Tumbush,
      published by Springer Publications, 2012, ISBN 978-1-4899-9500-1