SystemVerilog for Design
|Name of the course||Online||Lecture||Exercises||Lab|
|SystemVerilog for Design||✓||✓||✗||✓|
The course is a twelve-weeks training on the design flow of Application Specific Integrated Circuits (ASICs) with SystemVerilog. The course has a focus on the front-end design flow from HDL entry to synthesis and static timing analysis. It is recommended to have a solid knowledge in Digital Engineering and some basic experience in programming. The workload of the course depends on the study program. It is a clear objective of the course to be an online course.
The course is organized in two parts. Part One is a lecture on the Hardware Description Language (HDL) SystemVerilog with a focus on Register-Transfer-Level design and synthesis. Students design, simulate and test small designs at Register-Transfer-Level (RTL) as introduced in the course material. The respective test benches are at rudimentary level as they are normally expected from a design engineer to secure basic functionality. Part Two is a practical lab with a series of exercise on the digital ASIC design flow and standard procedures in this flow as they occur in large ASIC designs. The lab exercise is focused on RTL-synthesis, static timing analysis and timing debug, power profiling, logic equivalence check and the ECO flow.
The lab is built on the Cadence Design Environment. All laboratories are based on training materials used in industry - so called Rapid Adoption Kits (RAKs).
Successful candidates present a the results to the course members in a short presentation and pass an oral examination. Having completed the course successfully, students will understand the full ASIC design flow and will be able to work with the front-end design flow, implement RTL designs, run synthesis and static timing analysis and optimize the results. Verification is out of the scope of this course but there is a separate course SystemVerilog for Verification on this topic.
|1||Introduction to SystemVerilog||[PDF]|
|2||Modeling at Register-Transfer-Level||[PDF]|
|3||Net and variable types||[PDF]|
|4||Organizing designs with packages||[PDF]|
|5.1||SystemVerilog at Register-Transfer-Level (1 of 2)||[PDF]|
|5.2||SystemVerilog at Register-Transfer-Level (2 of 2)||[PDF]|
|6||Synthesis at Register-Transfer-Level||[PDF]|
|7||Modeling sequential logic and memory||[PDF]|
|8||Intentional and unintentional inferred latches||[PDF]|
|FLOW RAK||ASIC design flow example||[PDF*]|
|GENUS RAK||RTL Synthesis Compiler||[PDF*]|
|Tempus GTD RAK||Global Timing Debug||[PDF*]|
|RTL-VCD RAK||Power Profiling||[PDF*]|
|LEC RAK||Logic Equivalence Check||[PDF*]|
|ECO RAK||Engineering Change Orders (RTL to GDSII)||[PDF*]|
Literature RTL Modeling with SystemVerilog for Simulation and Synthesis, Stuart Sutherland,
published by Sutherland HDL, Oregon 2017, ISBN 078-1-5467-7634-5
 CMOS VLSI Design, Weste & Harris, Addison Wesley Publ., ISBN 0-321-54774-8