Prof. Dr. Matthias Fertig

Professor of Computer Engineering

Latest News

(08/2021) UDPMLab V2.01 released. Optimizations achieve a factor 10 to 500 speed-up in single thread performance for 3D scalar Wave Propagation Method. Publication pending.

(06/2021) Verigen with refined state transition coding, default pre-case assignments and support for design hierarchies available. Examples available for download.

(02/2021) UDPMLab V1.01 released. Optimizations for scalar 2D Beam Propagation Method achieve a single-thread run time reduction up to 75%. Publication pending.


Research & Development, Academic Education & Teaching

Compulsory subjects

Elective subjects (ASIC-Design)

Microprocessor architecture

Elective subjects (Optics and Photonics)

Cadence design framework

As an academic organization and user of a Cadence academic license agreement, we hereby make our work visible.

The ASIC design environment is used for educational purposes in lectures and student laboratories. Digital ASIC design is performed with the Cadence framework.

Students are trained on the front end design with HDL (VHDL or Verilog), simulation with INCISIVE, synthesis with GENUS and static timing analysis with TEMPUS.