Prof. Dr. Matthias Fertig

Professor of Computer Engineering

Latest News

MPC-group funded Xilinx Kintex Ultrascale FPGA evaluation board and host computer.

"Future Computer Hardware" Symposium 2020


Research & Development, Academic Education & Teaching

Compulsory subjects

Electrical Engineering 1 Lab

Elective subjects

Microprocessor architecture

Cadence design framework

As an academic organization and user of a Cadence academic license agreement, we hereby make our work visible.

The ASIC design environment is used for educational purposes in lectures and student laboratories. Digital ASIC design is performed with the Cadence framework.

Students are trained on the front end design with HDL (VHDL or Verilog), simulation with INCISIVE, synthesis with GENUS and static timing analysis with TEMPUS.